View AT25P1024_1229470.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features ? serial peripheral interface (spi) compatible supports spi modes 0 (0,0) and 3 (1,1) 2.1 mhz clock rate 128-byte page mode only for write operations low-voltage and standard-voltage operation ?2.7(v cc =2.7vto5.5v) block write protection ? protect 1/4, 1/2, or entire array write protect (wp ) pin and write disable instructions for both hardware and software data protection self-timed write cycle (5 ms typical) high reliability ? endurance: 100,000 write cycles ? data retention: >40 years 20-lead jedec soic and 8-lead leadless array package description the AT25P1024 provides 1,048,576 bits of serial electrically erasable programmable read only memory (eeprom) or ganized as 131,072 words of 8 bits each. the device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. the AT25P1024 is available in space saving 20-lead jedec soic and 8-lead lap packages. rev. 1082g?seepr?08/02 spi serial eeproms 1m (131,072 x 8) AT25P1024 pin configurations pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input nc no connect (continued) 20-lead soic 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 cs so nc nc nc nc nc nc wp gnd vcc hold nc nc nc nc nc nc sck si 8-lead leadless array bottom view 1 2 3 4 8 7 6 5 vcc hold sck si cs so wp gnd
2 AT25P1024 1082g?seepr?08/02 the AT25P1024 is enabled through the chip select pin (cs ) and accessed via a 3-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all programming cycles are completely self-timed, and no sep- arate erase cycle is required before write. block write protection is enabled by programming the status register with top ?, top ? or entire array of write protec- tion. separate program enable and program disable instructions are provided for additional data protection. hardware data protection is provided via the wp pin to protect against inadvertent write attempts to the status register. the hold pin may be used to suspend any serial communication without resetting the serial sequence. block diagram absolute maximum ratings* operating temperature .................................. -55 cto+125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 cto+150 c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma 131,072 x 8
3 AT25P1024 1082g?seepr?08/02 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il and v ih max are reference only and are not tested. pin capacitance (1) applicable over recommended operating range from t a =25 c,f=1.0mhz,v cc = +5.0v (unless otherwise noted). symbol test conditions max units conditions c out output capacitance (so) 8 pf v out =0v c in input capacitance (cs ,sck,si,wp ,hold )6pfv in =0v dc characteristics applicable over recommended operating range from: t ai =-40 cto+85 c, v cc =+2.7vto+5.5v, t ac =0 cto+70 c, v cc = +2.7v to +5.5v (unless otherwise noted). symbol parameter test condition min typ max units v cc1 supply voltage 2.7 5.5 v v cc2 supply voltage 4.5 5.5 v i cc1 supply current v cc =5.0vat1mhz,so=openread 2.0 5.0 ma i cc2 supply current v cc = 5.0v at 2 mhz, so = open write 4.0 7.0 ma i sb1 standby current v cc =2.7v,cs =v cc 0.2 3.0 a i sb2 standby current v cc =5.0v,cs =v cc 2.0 7.0 a i il input leakage v in =0vtov cc -3.0 3.0 a i ol output leakage v in =0vtov cc ,t ac =0 cto70 c -3.0 3.0 a v il (1) input low voltage -0.6 v cc x0.3 v v ih (1) input high voltage v cc x0.7 v cc +0.5 v v ol1 output low voltage 4.5v v cc 5.5v i ol =3.0ma 0.4 v v oh1 output high voltage i oh =-1.6ma v cc -0.8 v
4 AT25P1024 1082g?seepr?08/02 note: 1. this parameter is characterized and is not 100% tested. ac characteristics applicable over recommended operating range from t a =-40 cto+85 c, v cc = as specified, c l = 1 ttl gate and 100 pf (unless otherwise noted). symbol parameter voltage min max units f sck sck clock frequency 4.5 - 5.5 2.7 - 5.5 0 0 2.1 1.0 mhz t ri input rise time 4.5 - 5.5 2.7 - 5.5 2 2 s t fi input fall time 4.5 - 5.5 2.7 - 5.5 2 2 s t wh sck high time 4.5 - 5.5 2.7 - 5.5 200 400 ns t wl sck low time 4.5 - 5.5 2.7 - 5.5 200 400 ns t cs cs high time 4.5 - 5.5 2.7 - 5.5 250 500 ns t css cs setup time 4.5 - 5.5 2.7 - 5.5 100 250 ns t csh cs hold time 4.5 - 5.5 2.7 - 5.5 150 250 ns t su data in setup time 4.5 - 5.5 2.7 - 5.5 30 50 ns t h data in hold time 4.5 - 5.5 2.7 - 5.5 50 50 ns t hd hold setup time 4.5 - 5.5 2.7 - 5.5 100 100 ns t cd hold hold time 4.5 - 5.5 2.7 - 5.5 200 300 ns t v output valid 4.5 - 5.5 2.7 - 5.5 0 0 200 400 ns t ho output hold time 4.5 - 5.5 2.7 - 5.5 0 0 ns t lz hold to output low z 4.5 - 5.5 2.7 - 5.5 0 0 100 200 ns t hz hold to output high z 4.5 - 5.5 2.7 - 5.5 100 200 ns t dis output disable time 4.5 - 5.5 2.7 - 5.5 200 250 ns t wc writecycletime 4.5 - 5.5 2.7 - 5.5 5 10 ms endurance (1) 5.0v, 25 c, page mode 4.5 - 5.5 2.7 - 5.5 100k write cycles
5 AT25P1024 1082g?seepr?08/02 serial interface description master: the device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the AT25P1024 always operates as a slave. transmitter/receiver: the AT25P1024 has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code that defines the operations to be performed. invalid op-code: if an invalid op-code is received, no data will be shifted into the AT25P1024, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will reinitialize the serial communication. chip select: the AT25P1024 is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the serial output pin (so) will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the AT25P1024. when the device is selected and a serial sequence is underway, hold can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial communication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the write protect pin (wp ) will allow normal read/write operations when held high. when the wp pin is brought low and wpen bit is ?1?, all write opera- tions to the status register are inhibited. wp going low while cs is still low will interrupt a write to the status register. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit in the status register is ?0?. this will allow the user to install the AT25P1024 in a system with the wp pin tied to ground and still be able to write to the status register. all wp pin functions are enabled when the wpen bit is set to ?1?.
6 AT25P1024 1082g?seepr?08/02 spi serial interface master: microcontroller slave: AT25P1024 data out (mosi) data in (miso) serial clock (spi ck) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs si so sck cs
7 AT25P1024 1082g ? seepr ? 08/02 functional description the AT25P1024 is designed to interface directly with the synchronous serial peripheral interface (spi) of the 6800 type series of microcontrollers. the AT25P1024 utilizes an 8-bit instruction register. the list of instructions and their operation codes are contained in table 1. all instructions, addresses, and data are transferred with the msb first and start with a high-to-low transition. write enable (wren): the device will power up in the write disable state when v cc is applied. all programming instructions must therefore be preceded by a write enable instruction. write disable (wrdi): to protect the device against inadvertent writes, the write disable instruction disables all programming modes. the wrdi instruction is indepen- dent of the status of the wp pin. read status register (rdsr): the read status register instruction provides access to the status register. the ready/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. ta ble 1. instruction set for the AT25P1024 instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 x011 read data from memory array write 0000 x010 write data to memory array ta ble 2. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen x x x bp1 bp0 wen rdy
8 AT25P1024 1082g ? seepr ? 08/02 write status register (wrsr): the wrsr instruction allows the user to select one of four levels of protection. the AT25P1024 is divided into four array segments. top quarter (1/4), top half (1/2), or all of the memory segments can be protected. any of the data within any selected segment will therefore be read only. the block write protec- tion levels and corresponding status register control bits are shown in table 4. the three bits, bp0, bp1, and wpen are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. wren, t wc , rdsr). the wrsr instruction also allows the user to enable or disable the write protect (wp ) pin through the use of the write protect enable (wpen) bit. hardware write protection is enabled when the wp pin is low and the wpen bit is ? 1 ? . hardware write protection is disabled when either the wp pin is high or the wpen bit is ? 0. ? when the device is hard- ware write protected, writes to the status register, including the block protect bits and the wpen bit, and the block-protected sections in the memory array are disabled. writes are only allowed to sections of the memory which are not block-protected. note: when the wpen bit is hardware write protected, it cannot be changed back to ? 0 ? , as long as the wp pin is held low. ta ble 3. read status register bit definition bit definition bit 0 (rdy ) bit 0 = 0 (rdy ) indicates the device is ready. bit 0 = 1 indicates the write cycle is in progress. bit 1 (wen) bit 1 = 0 indicates the device is not writeenabled.bit1=1indicatesthe device is write enabled. bit 2 (bp0) see table 4. bit 3 (bp1) see table 4. bits 4-6 are 0s when device is not in an internal write cycle. bit 7 (wpen) see table 5. bits 0-7 are 1s during an internal write cycle. ta ble 4. block write protect bits level status register bits array addresses protected bp1 bp0 AT25P1024 000 none 1(1/4) 0 1 01800 - 01ffff 2(1/2) 1 0 010000 - 01ffff 3(all) 1 1 0000 - 01ffff ta ble 5. wpen operation wpen wp wen protectedblock s unprotectedblocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected
9 AT25P1024 1082g ? seepr ? 08/02 read sequence (read): reading the AT25P1024 via the so (serial output) pin requires the following sequence. after the cs line is pulled low to select a device, the read op-code is transmitted via the si line followed by the byte address to be read (refer to table 6). upon completion, any data on the si line will be ignored. the data (d7-d0) at the specified address is then shifted out onto the so line. if only one byte is to be read, the cs line should be driven high after the data comes out. the read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. write sequence (write): in order to program the AT25P1024, two separate instructions must be executed. first, the device must be write enabled via the write enable (wren) instruction. then a write (write) instruction may be executed. also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. during an internal write cycle, all commands will be ignored except the rdsr instruction. a write instruction requires the following sequence. after the cs line is pulled low to select the device, the write op-code is transmitted via the si line followed by the byte address and the data (d7-d0) to be programmed (refer to table 6). programming will start after the cs pin is brought high. (the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit. the ready/busy status of the device can be determined by initiating a read sta- tus register (rdsr) instruction. if bit 0 = 1, the write cycle is still in progress. if bit 0 = 0, the write cycle has ended. only the read status register instruction is enabled during the write programming cycle. the AT25P1024 is capable of a 128-byte page write operation only. content of the page in the array will not be guaranteed if less than 128 bytes of data is received (byte operation is not supported). after each byte of data is received, the seven low order address bits are internally incremented by one; the high order bits of the address will remain constant. if more than 128 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. the AT25P1024 is automat- ically returned to the write disable state at the completion of a write cycle. note: if the device is not write enabled (wren), the device will ignore the write instruction and will return to the standby state, when cs is brought high. a new cs fall- ing edge is required to re-initiate the serial communication. 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable ta ble 6. address key address AT25P1024 a n a 16 -a 0 don ? tcarebits a 23 -a 17 ta ble 5. wpen operation wpen wp wen protectedblock s unprotectedblocks status register
10 AT25P1024 1082g ? seepr ? 08/02 timing diagrams (for spi mode 0 (0, 0)) synchronous data timing wren timing wrdi timing so v oh v ol hi-z hi-z t v valid in si v ih v il t h t su t dis sck v ih v il t wh t csh cs v ih v il t css t cs t wl t ho
11 AT25P1024 1082g ? seepr ? 08/02 rdsr timing wrsr timing read timing cs sck 01234567891011121314 si instruction so 76543210 data out msb high impedance cs si sck high impedance instruction 3-byte address 01234 4 5 5 6 6 7 7 8 9 10 11 28 23 22 21 3 ... 21 321 0 0 29 30 31 32 33 34 35 36 37 38 so
12 AT25P1024 1082g ? seepr ? 08/02 write timing hold timing cs sck si so 3-byte address 1st byte data-in 128th byte data-in instruction high impedance 0123456789101128 232221 3 10 6543210 7 2 29 30 31 32 33 34 1051 1052 1054 1053 1055 so sck hold t cd t hd t hz t lz t cd t hd cs
13 AT25P1024 1082g ? seepr ? 08/02 note: for 2.7v devices used in the 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics tables. ordering information ordering code package operation range AT25P1024c1-10ci-2.7 AT25P1024w1-10si-2.7 8c1 20s2 industrial (-40 cto85 c) package type 8c1 8-pad, 0.300" wide, leadless array package (lap) 20s2 20-lead, 0.300" wide, plastic gull wing small outline package (jedec soic) options -2.7 low-voltage (2.7v to 5.5v)
14 AT25P1024 1082g ? seepr ? 08/02 packaging information 8c1 ? lap 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8cn1 , 8-lead (8 x 5 x 1.04 mm body), lead pitch 1.27 mm, leadless array package (lap) a 8cn1 11/13/01 pin1 corner marked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d common dimensions (unit of measure = mm) symbol min nom max note a 0.94 1.04 1.14 a1 0.30 0.34 0.38 b 0.36 0.41 0.46 1 d 7.90 8.00 8.10 e 4.90 5.00 5.10 e 1.27 bsc e1 0.60 ref l 0.62 0.67 0.72 1 l1 0.92 0.97 1.02 1 note: 1. metal pad dimensions.
15 AT25P1024 1082g ? seepr ? 08/02 20s2 ? jedec soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20s2 , 20-lead, 0.300" wide body, plastic gull wing small outline package (soic) 1/9/02 20s2 a l a1 end view side view top view h e b n 1 e a d c common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-013, variation ac for additional information. 2. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exc eed 0.15 mm (0.006") per side. 3. dimension "e" does not include inter-lead flash or protrusion. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "l" is the length of the terminal for soldering to a substrate. 5. the lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. a 0.0926 0.1043 a1 0.0040 0.0118 b 0.0130 0.0200 4 c 0.0091 0.0125 d 0.4961 0.5118 1 e 0.2914 0.2992 2 h 0.3940 0.4190 l 0.0160 0.050 3 e 0.050 bsc
printed on recycled paper. 1082g ? seepr ? 08/02 xm ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard warranty whichisdetailedinatmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com at m e l ? is the registered trademark of atmel. other terms and product names may be the trademarks of others.

▲Up To Search▲

Price & Availability of AT25P1024

	To Download AT25P1024 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .